Semiconductor development organizations at integrated device manufacturers (IDMs) and independent foundries spend significant resources developing the integrated sequence of process operations used to fabricate the chips (integrated circuits (ICs)) they sell from wafers (“wafers” are thin slices of semiconductor material, frequently, but not always, composed of silicon crystal). Large portions of these resources are spent on fabricating experimental wafers and associated measurement, metrology (“metrology” refers to specialized types of measurements conducted in the semiconductor industry) and characterization structures, all for the purpose of ensuring that the integrated sequence of processes produces the desired semiconductor device structures. These experimental wafers are used in a trial-and-error approach to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow. Due to the increasing complexity of advanced technology node process flows which can include large numbers of processes, a large portion of the experimental fabrication runs result in negative or null characterization results. These experimental runs are long in duration, weeks to months in the “fab” (fabrication environment), and expensive, as each experimental wafer may cost thousands of dollars. Recent semiconductor technology advances, including FinFET, TriGate, High-K/Metal-Gate, embedded memories and advanced patterning, have dramatically increased the complexity of integrated semiconductor fabrication processes. The cost and duration of technology development using this trial-and-error experimental methodology has concurrently increased.
A virtual fabrication environment for semiconductor device structures offers a platform for performing semiconductor process development at a lower cost and higher speed than is possible with conventional trial-and-error physical experimentation. A virtual fabrication environment is capable of virtually modeling an integrated process flow and predicting the complete 3-D structures of all devices and circuits that comprise a full technology suite. Virtual fabrication can be described in its most simple form as combining a description of an integrated process sequence with a subject design, in the form of 2D design data (masks or layout), and producing a 3-D structural model that is predictive of the result expected from a real/physical fabrication run. A 3-D structural model includes the geometrically accurate 3-D shapes of multiple layers of materials, implants, diffusions, etc. that comprise a chip or a portion of a chip. Virtual fabrication is done in way that is primarily geometric, however the geometry involved is instructed by the physics of the fabrication processes. By performing the modeling at the structural level of abstraction (rather than physics-based simulations), construction of the structural models can be dramatically accelerated, enabling full technology modeling, at a circuit-level area scale. The use of a virtual fabrication environment thus provides fast verification of process assumptions, and visualization of the complex interrelationship between the integrated process sequence and the 2D design data.